EDN

Logic 101 – Part 2 – Positive vs Negative Logic

1. Logical versus arithmetic views of a digital function. Having said this, it is generally preferable to employ a single consistent format to cover both cases, and it is easier to view logical ...
Electronic Design

Dirt Cheap ASIC Design for Dummies (Part 3): NMOS, PMOS Silicon Design Using a Web Browser

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...
Semiconductor Engineering

Stacking Logic On Logic

Advanced packaging can be an alphabet soup of possible approaches, from heterogenous integration of multiple die types into a single package, to three-dimensional stacking of multiple dies on top of ...
Semiconductor Engineering

Models for Both Strained and Unstrained GAA FETs Using Neural Networks

A new technical paper titled “Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach” was published by researchers at Hanyang University ...
Hackaday

Simulating High-Side Bootstrap Circuits With LTSpice

LTSpice is a tool that every electronics nerd should have at least a basic knowledge of. Those of us who work professionally in the analog and power worlds rely heavily on the validity of our ...
EDN

Positive, Negative, and Assertion-Level Logic

Although wrapping one’s brain around the concepts of positive, negative, and assertion-level logic can require some mental gymnastics, understanding these topics can be very rewarding. Although ...
Hackaday

Unusual Circuits In The Intel 386’s Standard Cell Logic

Intel’s 386 CPU is notable for being its first x86 CPU to use so-called standard cell logic, which swapped the taping out of individual transistors with wiring up standardized functional blocks. This ...