GOTHENBURG, Sweden--(BUSINESS WIRE)--Under a contract with the European Space Agency (ESA), Frontgrade Gaisler is designing a new RISC-V processor tailored to meet the requirements of microcontrollers ...
TOKYO--(BUSINESS WIRE)--Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today introduced the industry’s first RISC-V MCU specifically optimized for ...
The RISC-V CPU architecture currently accounts for under 1% of the world’s processor market, but that is going to change rapidly over the next years as its parallel processing is perfectly suited to ...
RISC-V, an open instruction set architecture (ISA), is reshaping the global computing landscape. Unlike proprietary ISAs such as x86, widely used by Intel and AMD, or ARM, which dominates mobile and ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
A team of engineers at Fudan University has successfully designed, built and run a 32-bit RISC-V microprocessor that uses molybdenum disulfide instead of silicon as its semiconductor component. Their ...
Thanks to RISC-V's open nature, more scrappy board developers can produce their own chips without signing legal agreements or ...
Qualcomm said Wednesday that it has acquired Ventana Micro Systems, a startup that was focused on developing server CPU ...
Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More Synopsys announced its plans for expanding its processor intellectual ...
SiFive, Inc. has unveiled its SiFive Performance P870-D data-center processor, targeting highly parallelizable infrastructure workloads such as video streaming, storage and web appliances. The ...
Why it matters: Arm and x86 processor architectures made a fair number of mistakes when first introduced to the market. You would think that developers working with the open-source RISC-V would have ...