EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
EDN

UVM Reactive agents verify with a handshake

UVM (Universal Verification Methodology) is widely used in creating object-oriented test environments. UVM provides two key benefits to verification engineers; one is reusability; the other is ...
EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Semiconductor Engineering

Best Practices In Verification

The advent of advanced verification methodologies such as the UVM and its predecessors VMM and OVM has changed the verification landscape in many ways. Design and verification teams used to worry ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
Yahoo Finance

Accellera Systems Initiative Releases UVM 1.2

NAPA, CA--(Marketwired - Jun 24, 2014) - Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...